RTL Design Engineer

Simulators & HLS · Brno, Brno
Department Simulators & HLS
Employment Type Full-Time
Minimum Experience Mid-level

 


YOUR ROLE:


  • Create RTL prototypes of new features in Codasip Studio

  • Work with AMBA buses (AHB, AXI, ACE)

  • Develop functional processor units (memory, cache, TCM, OCD, trace,…)

  • Extend on-chip debugger according to RISC-V Debug/Nexus /JTAG specification

  • Synthesize RTL code, analyze results, optimize

  • Work with tools for RTL code formal verification

  • Optimize and reduce energy consumption (low power) 


YOU SHOULD HAVE:


  • 2 years of experience (university internship in IT/electro field counts too)

  • Advanced knowledge of at least one HDL language (VHDL/Verilog/SystemVerilog)

  • Experience with HW synthesis tools for ASIC/FPGA (for example Xilinx ISE, Xilinx Vivado, Synopsys DC, Cadence RC/Genus)

  • Experience in HW design debugging (using a logic analyzer, ChipScope, JTAG, etc.)

  • Analytical thinking, self-sufficiency, team collaboration

  • At least passive knowledge of English


NICE-TO-HAVES: 


  • Familiarity with the area of computer systems and architectures

  • Knowledge of versioning tools (Git, SVN)

  • Experience with microcontroller programming (for example AVR/PIC/ARM/..., JTAG, OpenOCD)

  • Knowledge of C++


This position can be based in our R&D center in Brno or Prague or can be remote.

Thank You

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  • Location
    Brno, Brno
  • Department
    Simulators & HLS
  • Employment Type
    Full-Time
  • Minimum Experience
    Mid-level